- This topic has 8 replies, 3 voices, and was last updated 1 year, 7 months ago by
.
-
Posts
-
Hello,
We are working to deploy qty 4 P4 switches (EdgeCore Wedge with 100Gbps ports and a Tofino chipset). We are also deploying 25 Xilinx dual 100Gbps port U280 FPGAs (roughly one per site) for which a P4 toolchain exists (we are in the process of proving the toolchain). So the answer to your question depends entirely on what you are trying to do.
1 user thanked author for this post.
In addition Paul Ruth has developed soft p4 switch deployments that work in the VM today already. They use hardware interfaces (100Gbps and 25Gbps ports) depending on how you configure the VM.
We are working on it. We are port-constrained on our dataplane switches in a number of desirable locations. Once we are able to resolve those constraints we should be able to ship the switches out and add the necessary code support in the control framework to enable working with them.
I’m assuming you or your professor have signed the SLACA with Intel and have access to their compiler tools. This is not something we will be providing – we will be providing P4 switches with runtime that allows you remotely to load the bytecode, but compiling the code using Intel-licensed tools will be the user’s responsibility.
Once we are
Is there any update on deploying qty 4 P4 switches (EdgeCore Wedge with 100Gbps ports and a Tofino chipset). When is the estimated time to do the experiments?
Due to Intel’s announcement about stopping further development of the Tofino chipsets we’ve had to alter the strategy for deploying them. Previously we planned to have them at several core locations, but now we feel this is no longer warranted since these products have a limited useful lifespan, more likely now used for education, so instead we identified several campus sites and we are discussing the deployment with them.
- The topic ‘Is it possible to compile p4 program and do experiments with programmable switch’ is closed to new replies.