[Vitis Networking P4] Stateful packet processing on FPGAs

[Angelos Dimoglis]

Hello,

I am working on a demo for traffic redirection and I am using Vitis Networking P4 to program the FPGAs. The first FPGA on the topology is responsible for redirecting the traffic to the selected path. We would like the selected path to be stored on the FPGA, so every time the FPGA knows where to redirect the traffic. Let me note that our objective is to use in-network control messages to change the path, without involving the control plane. The thing is the register extern is not supported and I cannot find any other way keep & change state on the data plane using P4. Is there any workaround for this?

Thank you in advance.

 

Regards,

Angelos

[Mohammad Firas Sada]

This is a stateful extern example: https://github.com/esnet/esnet-smartnic-hw/tree/main/examples/p4_with_extern

[Angelos Dimoglis]

Hi Mohammad,

Oh, thank you! I will check it out.

 

Angelos

• This reply was modified 1 week, 6 days ago by Angelos Dimoglis.

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