[Komal Thareja]

Please share the slice ID. Slice ID can be captured from the Portal as well as from JH.

Portal -> Experiments -> My Slices -> Copy the Slice ID.

Also, how are you renewing the slices – Portal or JH?

Thanks,

Komal

[Komal Thareja]

Hi,

Could you please share your slice id?

Thanks,

Komal

[Komal Thareja]

Hi Ilya,

Thank you for reporting this issue. It seems to be a bug, and I’m in the process of debugging it. In the meantime, I’ve closed your slice, so it should no longer show up as “Configuring.”

Best regards,
Komal

[Komal Thareja]

Hi Vaneshi,

Permission updated would be rolled out with Release 1.8 in January.

Thanks,

Komal

[Komal Thareja]

Hi Sourya,

It looks like the authorized_keys file is not correct. I am not even able to login to nova SSH keys.

Could you please confirm if you see a key which ends with Generated-by-Nova  in /home/ubuntu/.ssh/authorized_keys ?

Also, please share the output of the command ls -ltr /home/ubuntu/.ssh/ ?

Thanks,

Komal

[Komal Thareja]

Correction: Both the CERN and CIEN racks have ConnectX-6 and GPU available on the same host. However, the CIEN rack is currently under maintenance as it is being transported back from SC.

You can proceed with your experiment on the CERN rack, subject to its availability.

Additionally, here’s a Fablib code snippet to help you check for specific resources on hosts:


fields=['name','nic_connectx_6_capacity','nic_connectx_5_capacity','tesla_t4_capacity','rtx6000_capacity', 'a30_capacity', 'a40_capacity']
output_table = fablib.list_hosts(fields=fields)


Thanks,
Komal

1 user thanked author for this post.

Tanay Maheshwari

[Komal Thareja]

Hi Tanay,

As you mentioned, the current infrastructure supports GPUs with ConnectX-5. Unfortunately, GPUs with ConnectX-6 are not a feasible option at this time. I hope the available setup works well for your experiment.

Thanks,
Komal

[Komal Thareja]

Shared the BitFile flash status with Nishanth over email. He confirmed that FPGA slice with EsNet Sites are working as expected.

Thanks,
Komal

[Komal Thareja]

Hi Vaneshi,

We are working to update the Permissions, but in the current release, you need permission Net.PortMirroring for InSlice PortMirroring to work.

Thanks,
Komal

[Komal Thareja]

Hi Vaneshi,

Your project would need Net.PortMirroring permission for this to work. Could you please check if your project has this permission? If not, Please request your Project Owner or Lead to request for these permissions from the portal.
More details for requesting the permissions can be found here.

Thanks,
Komal

[Komal Thareja]

Hi Nishanth,

I will check other sites too, it would be helpful if you can share sites you tried.
Could you please delete your slice and try again?

It might be related to which bitfile has been used to Flash the FPGA. For instance, INDI is flashed with a bit file compatible with NEU workflow.

Thanks,
Komal

• This reply was modified 1 year, 7 months ago by Komal Thareja.

[Komal Thareja]

Hi Yuanjun,

Details about the VM profiles are available here. For specific flavor information, please refer to the GitHub link. Feel free to reach out if you have any questions or concerns.

Thanks,

Komal

[Komal Thareja]

Hi Sourya,

I can confirm both node: MICH_3D and network interconnect4 have been deleted and are in Closed State.
In order to move the slice from ModifyError to StableError state, please execute the following block of code:


slice = fablib.get_slice(name=”Tailscale_Mesh_VPN”)
slice.modify_accept()


This should allow you to do any additional modifications.

Thanks,
Komal

[Komal Thareja]

Hi Ilya,

I’ve confirmed that the FPGA is currently allocated to a slice belonging to another user. While the FPGA may have been flashed with your bitfile, our current allocation system does not reserve FPGAs for projects based on bitfiles flash requests. If the FPGAs are not linked to a specific slice, they remain available for other users to request and utilize.

We are actively working on enhancing our allocation system and quota management, and I will take your experience as valuable feedback for these improvements. Apologies for any inconvenience this may have caused.

Thanks,
Komal

[Komal Thareja]

KANS and LOSA both have the FPGA allocated.
WASH seems to have the FPGA available but based on the Core/Ram/Disk requested, the slice might have been rejected.
Snapshot for WASH:

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